Many system busses are cache line-oriented and do not support memory requests beginning at arbitrary byte locations. Each memory request fetches an entire cache line by addressing the first byte of the line. Packets transmitted on a network, however, include a payload of data which can begin at any arbitrary byte address. Thus, if the packet payload is to begin with a byte of data in the middle of a cache line, extra complexity is involved in building a packet. When data is returned from memory as a line, the network adapter needs to be instructed to copy only the desired data into a temporary buffer which we call herein a packet buffer. A packet buffer is organized with lines of data beginning at the first byte of the packet payload which is not necessarily the first byte of a cache line. When the logic unit that makes the memory request is different from the logic unit that controls the packet buffer, it is typically necessary to first communicate an indication of the difference between the first byte of the packet payload and the first byte of a cache line. Thereafter, memory requests can be made and the packet buffer can be properly loaded.
If the first byte of the packet payload is not the first byte of the cache line, the cache line after shifting will need to be split across two line locations in the packet buffer. In a conventional packet buffer that receives a line of data at a time, two write cycles will be needed to store a cache data line in the packet buffer.